1. Field of the Invention
The present invention generally relates to electronic circuits and, more particularly, to a circuit and technique for generating a pair of differential signals from a single ended signal.
2. Description of the Related Art
To meet the computing industry's growing demands for high speed data transfer between components, many systems forego conventional parallel buses to high speed synchronous serial buses. In such systems, data is transferred between devices on a serial bus, synchronized to a clock signal. For example, in a gaming system, such a serial bus may be used to transfer data between a central processing unit (CPU) and a graphics processing unit (GPU). A receiving component will typically transfer the serially received data to some component for de-serialization, converting the serial data into for presentation on wider internal buses for efficient processing. For example, data transferred over a high speed serial 8-bit bus may be processed internally using a 64-bit bus.
In some cases, in order to route data internally (e.g., for serialization or de-serialization) single ended signals may be converted to differential signal. By utilizing lower voltage swings than single ended signals, differential signals can generally provide higher data throughput. This is possible because the differential threshold in a differential receiver is typically more easily controlled than the threshold of a single transistor. The lower voltage swings can also result in reduced power consumption and reduced switching noise and crosstalk, as the opposite currents carried on differential signal traces tend to cancel the electric and magnetic fields.
FIG. 1 illustrates an exemplary conventional differential signal driver circuit 100 for generating a pair of differential signals OUTX and OUTY from a single ended input signal XIN. As illustrated, switching signals X1 and XB may be generated from the input signal XIN via a pair of inverters 112 and 114, respectively. These switching signals may be used to control the switching of transistors 102 and 104. A bias voltage VBIAS applied to a transistor 106 may be used to control the total current flowing through the switching transistors 102 and 104. Load resistors 108 may be sized accordingly to the impedance of the transmission line.
Operation of the driver circuit 100 may be explained with reference to the timing diagrams 200 and 210 shown in FIG. 2. Waveforms for signals X1 and XB are shown as waveforms 202 and 204, respectively. Waveforms for the differential output signals OUTX and OUTY are shown as waveforms 214 and 212, respectively The illustrated example assumes that the input signal XIN begins in an initial low state. Consequently, X1 is in a high state and XB is in a low state, causing transistor 102 to be turned on and transistor 104 to be turned off. As a result, node X is pulled down, keeping differential signal OUTX in a low initial state, while node Y is pulled up, keeping differential signal OUTY in a high initial state.
XIN then transitions to a high state, causing X1 to begin transitioning to a low state, at a time t0. Once X1 falls below a switching threshold of transistor 102, at time t1, transistor 102 will turn off and node X will begin charging, causing OUTX to transition to a high state. Due to the delay associated with the inverter 114, XB will not begin transitioning to a high state until a time t2 after X1 has begun transitioning. As a result, XB will not reach a switching threshold of transistor 104, until a later time t3, finally causing transistor 104 to turn on and node Y to begin discharging, bringing OUTY to a low state, which is finally reached at t4.
The differential signal pair OUTX and OUTY is typically routed to a receiver at some other location on a circuit board that converts the differential signal pair back to a single ended signal. Unfortunately, the delay D between switching of differential signals OUTX and OUTY, caused by the inverter delay between switching signals X1 and XB, can result in duty cycle distortion. In other words, the single ended signal generated by the receiver may have an asymmetrical duty cycle, for example, assuming an input signal pattern alternating between high and low states, with one logic state of the signal waveform being greater than the other. In some cases, the single ended signal generated by the receiver may be synchronized with a clock signal having a symmetrical (50%) duty cycle for high and low states. In such cases, the asymmetry of the logic states may result in reduced timing margins.
Accordingly, what is needed is a technique for generating a pair of differential signals with balanced switching between logical states.